1. Field of the Invention
The present invention relates to a method and apparatus for determining tap coefficients in phase locking in reproducing recorded or transmitted digital data and to a method and apparatus for performing phase locking in reproducing recorded or transmitted digital data.
2. Description of the Related Art
A storage device using magnetic or optical recording technology or the like has an analog signal processing block including an analog circuit and a digital signal processing block including a digital circuit, which are circuits for playing back a recorded signal.
Due to recent developments in semiconductor manufacturing technology, the size and the speed of a digital circuit portion in a large-scale integrated circuit (LSI) are increasing. In such a particularized semiconductor manufacturing process, an analog circuit portion has a large influence on the cost performance since the analog circuit portion occupies a large area on a chip, and there is a growing demand to reduce the scale of the analog circuit portion. A high-performance digital signal processor that previously could not be mounted onto a circuit due to the circuit scale and the cost can now actually be mounted. One such example is a digital phase-locked loop (PLL) circuit.
As an example of the configuration of a digital PLL circuit, a digital signal processing PLL circuit using an interpolated timing recovery (ITR) scheme (may also be referred to as an “ITR digital PLL circuit”) has been widely put to practical use. Applications of such an ITR digital PLL circuit in the field of reproducing magnetically recorded data are described in articles entitled “A MMSE Interpolated Timing Recovery Scheme for the Magnetic Recording Channel”, Zi-Ning Wu, John M. Cioffi, et al., Communications, 1997, ICC '97 Montreal, Towards the Knowledge Millennium, 1997 IEEE International Conference on, Vol. 3, 1997, pp. 1625-1629 Vol. 3, and “Interpolated Timing Recovery for Hard Disk Drive Read Channels”, Mark Spurbeck and Richard T. Behrens, Communications, 1997, ICC '97 Montreal, Towards the Knowledge Millennium, 1997 IEEE International Conference on, Vol. 3, 1997, pp. 1618-1624 Vol. 3. The ITR scheme can also be easily applied to a reproducing architecture for playing magnetically or optically recorded signals.
FIG. 27 shows an example of the configuration of an optical disk player including an ITR digital PLL circuit.
An optical disk reproduced signal processor 101 includes, as shown in FIG. 27, an analog anti-aliasing filter 102, an analog-to-digital (A/D) converter 103 that performs analog-to-digital conversion, a digital equalization filter 104 that performs equalization, and an ITR digital PLL circuit 110.
The ITR digital PLL circuit 110 includes a phase interpolation filter 111 that interpolates the output of the digital equalization filter 104, a phase error calculator 112 that calculates a phase error between the input and the output of the phase interpolation filter 111, a digital loop filter 113 that filters an output signal of the phase error calculator 112, a phase integrator 114 that integrates an output signal of the digital loop filter 113, and an interpolation tap coefficient read-only memory (ROM) 115 that stores interpolation tap coefficients and that generates and outputs interpolation tap coefficients necessary according to an output value of the phase integrator 114 to the phase interpolation filter 111.
A reproduced signal r(k) is input from an optical disk to the optical disk reproduced signal processor 101.
The input reproduced signal r(k) is anti-aliased by the analog anti-aliasing filter 102, and thereafter is sampled by the A/D converter 103 at a frequency fs=α·fd (α>1.0), which is slightly higher than a data rate frequency fd. The sampled reproduced signal r(k) is input to the digital equalization filter 104 and equalized according to a desired equalization scheme, and thereafter, the equalized signal is input to the digital PLL circuit 110. The desired equalization scheme is a partial response (PR) equalization target or the like for use in general digital signal processing.
The digital PLL circuit 110 performs phase locking of the reproduced signal r(k) by shifting the phase by a desired amount and outputs an output signal y(k) synchronized in phase with the reproduced signal r(k). The ITR digital PLL circuit 110 decimates the signal, that is, obtains only a necessary signal and discards an unnecessary signal generated due to a difference between the data rate frequency fd and the sampling frequency fs by estimating a point at which a signal mismatching occurs, that is, a point at which there is a phase jump.
Various methods have been proposed to interpolate sampled data in the ITR digital PLL circuit 110. When phase interpolation is achieved using a finite impulse response (FIR) filter, a sinc function, a sinc function multiplied by various window functions for use in digital signal processing, or the like is generally used as interpolation tap coefficients of the FIR filter.
However, these interpolation tap coefficients implement a filter that basically has low-pass frequency characteristics and are not often used in, for example, active equalization for amplifying high frequency components of a signal. This is because, in order to design an interpolation filter with strictly determined frequency characteristics, it is necessary to fully understand the relationship between the data rate frequency fd and the sampling frequency fs.
In known optical disk players or the like, an equalizing circuit is provided, apart from the digital PLL circuit 110, to implement partial response equalization.
As an example of an equation to calculate a phase error for use in a partial-response-equalized data signal sequence, a timing gradient equation shown in the following equation (1) is described in “A PRML System for Digital Magnetic Recording”, Roy D. Cideciyan, F. Dolivo, et al., IEEE Journal on Selected Areas in Communications, Vol. 10, No. 1, January 1992, pp. 38-56:Δτ(k)=−ŷ(k)·y(k−1)+ŷ(k−1)·y(k)  (1)                Δτ(k): calculated amount of phase error at time k        y(k): PLL output at time k        ŷ(k): ideal partial-response-equalized signal output estimated from y(k) at time k        
In the case of a system for calculating a phase error using equation (1), it is necessary that a PLL output signal be accurately equalized to a desired partial response signal. In order to achieve this accurate equalization, in the related art, as shown in FIG. 27, a digital equalization filter (FIR-type, infinite impulse response (IIR) type, or the like) has been provided at a stage subsequent to the A/D converter 103 and prior to the digital PLL circuit 110, or alternatively, as shown in FIG. 28, an analog equalization filter 105 has been provided at a stage prior to the A/D converter 103, thereby equalizing a signal to a partial response signal.
It is a difficult determining problem to achieve an optimal equalization performance using the analog equalization filter 105. When the digital equalization filter 104 is used equivalent architectures are present in both the digital equalization filter 104 and, at a subsequent stage, the phase interpolation filter 111 in the digital PLL circuit 110 for performing digital PLL processing. Thus, the circuit scale is increased.